1. Field of the Invention
The invention relates to an apparatus and a related method of coordinating a north bridge and a south bridge for controlling power saving state transition of a central processing unit, more particularly, to an apparatus and a related method for a connected indicator wire of an open-drain configuration set between the north bridge and the south bridge for coordinating a central processing unit in switching C2/C3 power saving states to support a bus master service.
2. Description of the Prior Art
A computer system is one of the important pieces of hardware in modern information era. Modern computer systems improve efficiency and also reduce power consumption. Thus manufacturers of this field tend to reduce power consumption and regard power issues as an important research and development topic.
In the computer system, the central processing unit controls management and operation of data and figures. The north bridge and the south bridge form a chipset responsible for managing data exchange between the central processing unit and other peripheral devices. For example, through a bus, the north bridge is coupled to a system memory and display accelerated graphics card, and the south bridge is coupled to peripheral devices such as a hard disk, optical disc drive, keyboard, mouse, etc. As the central processing unit controls the entire operation of the computer system, in order to reduce its power consumption, the modern central processing unit is capable of functioning at different states for power saving. Those skilled in the art will recognize that the modern computer processing unit operates at states C0, C1, C2, C3, C4 and C5 from a low to high state of power saving. At state C0 where the consumption is highest, the central processing unit exploits its full capability in operation and control, and is capable of receiving and transmitting all commands, signals and timing. In the higher state C1, the central processing unit enters a halt state and stops sending commands. The central processing unit here does not operate with the full capability as it does in state C0, thus requires less power consumption. In comparison, in the higher state C2, the central processing unit stops executing commands, only maintains an operating phase-locked loop (PLL), content recorded in cache of the central processing unit is also maintained. In another words, under the state C2, the central processing unit has less functional circuits than C1, but has a lower power consumption than C1.
Likewise, in state C3, the central processing unit stops the operation of the phase-locked loop in order to save more power; under the state C3, the power consumption of the central processing unit has decreased to ⅕˜ 1/10 of state C1 power consumption. When the central processing unit enters state C4 or C5, the central processing unit has even less power consumption and fewer functional circuits.
The higher the power saving state the central processing unit enters, the lower the power consumption, however, in order to allow the computer system to function properly, the central processing unit first needs to switch the power saving states in order to support certain functions. For example, when the peripheral devices of the north bridge and the south bridge need to access data stored in the system memory, they can request the south bridge to directly access memory through the north bridge, this is known as a bus master. In processing the bus master for the peripheral device, the north bridge and the south bridge manage the exchange of data between the peripheral device and system memory, and also the north bridge performs a snoop operation onto the central processing unit (to check whether the cache has this same data), to ensure the data in the cache and the system memory is the same. As known by those skilled in the art, when the central processing unit is executing a program and managing the data, the data needed is loaded from the system memory to the cache in the central processing unit. This is to accelerate accessing speed of data. However, when the central processing unit updates the data in the cache, the corresponding data in the system memory is not updated immediately. At this time, if a peripheral device transmits a bus master to directly access the system memory, the old data (not updated data) will be accessed. To avoid fetching the old data, during a bus master request of the peripheral device, the north bridge provides a snoop operation service to check if there is a copy or modified data in the cache to ensure that the data accessed by the peripheral device has the correct content. In order to support the snoop operation by the north bridge in the above-mentioned scenario, whenever there is a bus master request by the peripheral device, the central processing unit has to operate at or below state C2. If the central processing unit operates at state C3 or higher power saving states, then the north bridge cannot support the snoop operation service.
In the prior art, in order to support the related bus master request, the central processing unit needs to refresh at state C0, as described in the following. At state C3, a bus master requested by the peripheral device is transmitted to the south bridge, the north bridge sets the control signals, sequentially, STPCLK# (# means the opposition of STPCLK) and SLP# to change from 0 to 1. In this way, the central processing unit switches from state C3 to fully operational state C0. At state C0, the central processing unit is capable of changing contents of a register, and a register IO22 (or ARB_DIS) of the south bridge switches from 1 to 0, which ensures that the north bridge switches from state C3 to state C2 and below so that the snoop service can be performed, also means the north bridge and the central processing unit are capable of performing the snoop service. After register IO22 is changed, the south bridge can begin managing the bus master of the peripheral device and the snoop operation can be provided by the north bridge.
There is a drawback in the above-mentioned prior art, namely, the central processing unit is unable to reduce power consumption. Actually, the central processing unit can support snooping of the north bridge at state C2. However, in the prior art mentioned above, since the central processing unit can change the status of the register IO22 only at state C0, the central processing unit has to be switched to state C0. Except changing the register IO22, the bus master request of the peripheral device only involves the north bridge and the south bridge, not the central processing unit. Therefore in the above-mentioned the prior art of switching to state C0 in the central processor unit actually causes unnecessary high consumption of power.